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ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-70
ID073015 Non-Confidential
Figure 4-46 VAL Debug Request Enable Set Register bit assignments
Table 4-47 shows the VAL Debug Request Enable Set Register bit assignments.
To access the nVAL Debug Request Enable Set Register, read or write CP15 with:
MRC p15, 0, <Rd>, c15, c1, 3 ; Read nVAL Debug Request Enable Set Register
MCR p15, 0, <Rd>, c15, c1, 3 ; Write nVAL Debug Request Enable Set Register
On reads, this register returns the current setting. On writes, interrupt requests can be enabled
by writing a 1 to the appropriate bits. If a debug request is enabled, it is disabled by writing to
the nVAL Debug Request Enable Clear Register. See c15, VAL Debug Request Enable Clear
Register on page 4-73.
If one or more of the reset request fields (P2, P1, P0, and C) is enabled, and the corresponding
counter overflows, then a debug reset request is indicated by VALEDBGRQ being asserted
HIGH. This signal can be passed to an external debugger.
c15, nVAL IRQ Enable Clear Register
The nVAL IRQ Enable Clear Register characteristics are:
Purpose Disables overflow IRQ requests from any of the PMXEVCNTR Registers,
PMXEVCNTR0-PMXEVCNTR2, and PMCCNTR, for which they have
been enabled.
Usage constraints The nVAL IRQ Enable Clear Register is:
• A read/write register.
• Always accessible in Privileged mode. The PMUSERENR Register
determines access in User mode, see c9, User Enable Register on
page 6-15.
Configurations Available in all processor configurations.
Attributes See Table 4-48 on page 4-71.
Figure 4-47 on page 4-71 shows the nVAL IRQ Enable Clear Register bit assignments.
C
31 3210
Reserved
P2
P1
P0
Performance monitor counter
overflow debug request enables
Cycle count overflow debug request enable
Table 4-47 VAL Debug Request Enable Set Register bit assignments
Bits Name Function
[31] C PMCCNTR overflow debug request
[30:3] - UNP or SBZP
[2] P2 PMC2 overflow debug request
[1] P1 PMC1 overflow debug request
[0] P0 PMC0 overflow debug request
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