System Control
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-71
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Figure 4-47 nVAL IRQ Enable Clear Register bit assignments
Table 4-48 shows the nVAL IRQ Enable Clear Register bit assignments.
To access the nVAL IRQ Enable Clear Register, read or write CP15 with:
MRC p15, 0, <Rd>, c15, c1, 4 ; Read nVAL IRQ Enable Clear Register
MCR p15, 0, <Rd>, c15, c1, 4 ; Write nVAL IRQ Enable Clear Register
On reads, this register returns the current setting. On writes, overflow interrupt requests that are
enabled can be disabled by writing a 1 to the appropriate bits.
For more information of how to enable IRQ requests on counter overflows, and how the requests
are signaled, see c15, nVAL IRQ Enable Set Register on page 4-66.
c15, nVAL FIQ Enable Clear Register
The nVAL FIQ Enable Clear Register characteristics are:
Purpose Disables overflow FIQ requests from any of the PMXEVCNTR Registers,
PMXEVCNTR0-PMXEVCNTR2, and PMCCNTR, that are enabled.
Usage constraints The nVAL FIQ Enable Clear Register is:
• A read/write register.
• Always accessible in Privileged mode. The PMUSERENR Register
determines access in User mode, see c9, User Enable Register on
page 6-15.
Configurations Available in all processor configurations.
Attributes See Table 4-49 on page 4-72.
Figure 4-48 on page 4-72 shows the nVAL FIQ Enable Clear Register bit assignments.
C
31 3210
Reserved
P2
P1
P0
Performance monitor counter
overflow IRQ request disables
Cycle count overflow
IRQ request disable
Table 4-48 nVAL IRQ Enable Clear Register bit assignments
Bits Name Function
[31] C PMCCNTR overflow IRQ request
[30:3] - UNP or SBZP
[2] P2 PMC2 overflow IRQ request
[1] P1 PMC1 overflow IRQ request
[0] P0 PMC0 overflow IRQ request
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