System Control
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-66
ID073015 Non-Confidential
4.3.29 Validation Registers
The processor implements a set of validation registers. This section describes:
• c15, nVAL IRQ Enable Set Register
• c15, nVAL FIQ Enable Set Register on page 4-67
• c15, nVAL Reset Enable Set Register on page 4-68
• c15, VAL Debug Request Enable Set Register on page 4-69
• c15, nVAL IRQ Enable Clear Register on page 4-70
• c15, nVAL FIQ Enable Clear Register on page 4-71
• c15, nVAL Reset Enable Clear Register on page 4-72
• c15, VAL Debug Request Enable Clear Register on page 4-73
• c15, Cache Size Override Register on page 4-74.
c15, nVAL IRQ Enable Set Register
The nVAL IRQ Enable Set Register characteristics are:
Purpose Enables any of the PMXEVCNTR Registers,
PMXEVCNTR0-PMXEVCNTR2, and PMCCNTR, to generate an
interrupt request on overflow. If enabled, the interrupt request is signaled
by nVALIRQ being asserted LOW.
Usage constraints The nVAL IRQ Enable Set Register is:
• A read/write register.
• Always accessible in Privileged mode. The PMUSERENR Register
determines access in User mode, see c9, User Enable Register on
page 6-15.
Configurations Available in all processor configurations.
Attributes See Table 4-44.
Figure 4-43 shows the nVAL IRQ Enable Set Register bit assignments.
Figure 4-43 nVAL IRQ Enable Set Register bit assignments
Table 4-44 shows the nVAL IRQ Enable Set Register bit assignments.
C
31 3210
Reserved
P2
P1
P0
Performance monitor counter
overflow IRQ request enables
Cycle count overflow IRQ request enable
Table 4-44 nVAL IRQ Enable Set Register bit assignments
Bits Name Function
[31] C PMCCNTR overflow IRQ request
[30: 3] - UNP or SBZP
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