System Control
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-67
ID073015 Non-Confidential
To access the nVAL IRQ Enable Set Register, read or write CP15 with:
MRC p15, 0, <Rd>, c15, c1, 0 ; Read nVAL IRQ Enable Set Register
MCR p15, 0, <Rd>, c15, c1, 0 ; Write nVAL IRQ Enable Set Register
On reads, this register returns the current setting. On writes, interrupt requests can be enabled
by writing a 1 to the appropriate bits. If an interrupt request is enabled it is disabled by writing
to the nVAL IRQ Enable Clear Register, see c15, nVAL IRQ Enable Clear Register on
page 4-70.
If one or more of the IRQ request fields (P2, P1, P0, and C) is enabled, and the corresponding
counter overflows, then an IRQ request is indicated by nVALIRQ being asserted LOW. This
signal might be passed to a system interrupt controller.
c15, nVAL FIQ Enable Set Register
The nVAL FIQ Enable Set Register characteristics are:
Purpose Enables any of the PMXEVCNTR Registers,
PMXEVCNTR0-PMXEVCNTR2, and PMCCNTR, to generate an fast
interrupt request on overflow. If enabled, the interrupt request is signaled
by nVALFIQ being asserted LOW.
Usage constraints The nVAL FIQ Enable Set Register is:
• A read/write register.
• Always accessible in Privileged mode. The PMUSERENR Register
determines access in User mode, see c9, User Enable Register on
page 6-15.
Configurations Available in all processor configurations.
Attributes See Table 4-45 on page 4-68.
Figure 4-44 shows the nVAL FIQ Enable Set Register bit assignments.
Figure 4-44 nVAL FIQ Enable Set Register bit assignments
[2] P2 PMC2 overflow IRQ request
[1] P1 PMC1 overflow IRQ request
[0] P0 PMC0 overflow IRQ request
Table 4-44 nVAL IRQ Enable Set Register bit assignments (continued)
Bits Name Function
C
31 3210
Reserved
P2
P1
P0
Performance monitor counter
overflow FIQ request enables
Cycle count overflow FIQ request enable
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