System Control
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-68
ID073015 Non-Confidential
Table 4-45 shows the nVAL FIQ Enable Set Register bit assignments.
To access the FIQ Enable Set Register, read or write CP15 with:
MRC p15, 0, <Rd>, c15, c1, 1 ; Read FIQ Enable Set Register
MCR p15, 0, <Rd>, c15, c1, 1 ; Write FIQ Enable Set Register
On reads, this register returns the current setting. On writes, interrupt requests can be enabled
by writing a 1 to the appropriate bits. If an interrupt request is enabled it is disabled by writing
to the FIQ Enable Clear Register, see c15, nVAL FIQ Enable Clear Register on page 4-71.
If one or more of the FIQ request fields (P2, P1, P0, and C) is enabled, and the corresponding
counter overflows, then an FIQ request is indicated by nVALFIQ being asserted LOW. This
signal can be passed to a system interrupt controller.
c15, nVAL Reset Enable Set Register
The nVAL Reset Enable Set Register is:
• A read/write register.
• Always accessible in Privileged mode. The PMUSERENR Register determines access in
User mode, see c9, User Enable Register on page 6-15.
The nVAL Reset Enable Set Register characteristics are:
Purpose Enables any of the PMXEVCNTR Registers,
PMXEVCNTR0-PMXEVCNTR2, and PMCCNTR, to generate a reset
request on overflow. If enabled, the reset request is signaled by
nVALRESET being asserted LOW.
Usage constraints The nVAL Reset Enable Set Register is:
• A read/write register.
• Always accessible in Privileged mode. The PMUSERENR Register
determines access in User mode, see c9, User Enable Register on
page 6-15.
Configurations Available in all processor configurations.
Attributes See Table 4-46 on page 4-69.
Figure 4-45 on page 4-69 shows the nVAL Reset Enable Set Register bit assignments.
Table 4-45 nVAL FIQ Enable Set Register bit assignments
Bits Name Function
[31] C PMCCNTR overflow FIQ request
[30:3] - UNP or SBZP
[2] P2 PMC2 overflow FIQ request
[1] P1 PMC1 overflow FIQ request
[0] P0 PMC0 overflow FIQ request
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