System Control
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-72
ID073015 Non-Confidential
Figure 4-48 nVAL FIQ Enable Clear Register bit assignments
Table 4-49 shows the nVAL FIQ Enable Clear Register bit assignments.
To access the FIQ Enable Clear Register, read or write CP15 with:
MRC p15, 0, <Rd>, c15, c1, 5 ; Read FIQ Enable Clear Register
MCR p15, 0, <Rd>, c15, c1, 5 ; Write FIQ Enable Clear Register
On reads, this register returns the current setting. On writes, overflow interrupt requests that are
enabled can be disabled by writing a 1 to the appropriate bits.
For information on how to enable FIQ requests on counter overflows, and how the requests are
signaled, see c15, nVAL FIQ Enable Set Register on page 4-67.
c15, nVAL Reset Enable Clear Register
The nVAL Reset Enable Clear Register characteristics are:
Purpose Disables overflow reset requests from any of the PMXEVCNTR
Registers, PMXEVCNTR0-PMXEVCNTR2, and PMCCNTR, that are
enabled.
Usage constraints The nVAL Reset Enable Clear Register is:
• A read/write register.
• Always accessible in Privileged mode. The PMUSERENR Register
determines access in User mode, see c9, User Enable Register on
page 6-15.
Configurations Available in all processor configurations.
Attributes See Table 4-50 on page 4-73.
Figure 4-49 on page 4-73 shows the nVAL Reset Enable Clear Register bit assignments.
C
31 3210
Reserved
P2
P1
P0
Performance monitor counter
overflow FIQ request disables
Cycle count overflow
FIQ request disable
Table 4-49 nVAL FIQ Enable Clear Register bit assignments
Bits Name Function
[31] C PMCCNTR overflow FIQ request
[30:3] - UNP or SBZP
[2] P2 PMC2 overflow FIQ request
[1] P1 PMC1 overflow FIQ request
[0] P0 PMC0 overflow FIQ request
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