System Control
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-75
ID073015 Non-Confidential
Table 4-52 shows the Cache Size Override Register bit assignments.
Table 4-53 shows the encodings for the instruction and data cache sizes.
To access the Cache Size Override Register, write CP15 with:
MCR p15, 0, <Rd>, c15, c14, 0 ; VAL Cache Size Override Register
The Cache Size Override Register can only be used to select cache sizes for which the
appropriate RAM is integrated. Larger cache sizes require deeper data and tag RAMs, and
smaller cache sizes require wider tag RAMs. Therefore, it is unlikely that you can change the
cache size using this register except using a simulation model of the cache RAMs.
4.3.30 Correctable Fault Location Register
The CFLR characteristics are:
Purpose Indicates the location of the last correctable error that occurred during
cache or TCM operations.
Usage constraints The CFLR is:
• a read/write register
• accessible in Privileged mode only
• not updated on:
— speculative accesses, for example, an instruction fetch for an
instruction that is not executed because of a previous branch
— a TCM external error or external retry request.
• updated on:
— parity or ECC errors in the instruction cache
— single-bit ECC errors in the data cache
— parity or multi-bit errors in the data cache when write-through
behavior is forced
Table 4-52 Cache Size Override Register bit assignments
Bits Name Function
[31:8] - SBZ.
[7:4] Dcache Defines the data cache size override value. See Table 4-53.
[3:0] Icache Defines the instruction cache size override value. See Table 4-53.
Table 4-53 instruction and data cache size encodings
Encoding Instruction and data cache size
b0000 4kB
b0001 8kB
b0011 16kB
b0111 32kB
b1111 64kB
To Next Page
Loading...
