System Control
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-76
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— single-bit TCM ECC errors.
• updated by the processor, regardless of whether an abort is taken or
an access is retried in response to the error.
Configurations Available in all processor configurations.
Attributes See Table 4-54.
Every correctable error that causes a CFLR update also has an associated event. See Table 6-1
on page 6-2 for the events that are related to CFLR updates. If two correctable errors occur
simultaneously, for example an AXI slave error and an LSU or PFU error, the LSU or PFU write
takes priority. If multiple errors occur, the value in the CFLR reflects the location of the latest
event.
The same register is updated by all correctable errors. You can read bits [25:24] to determine
whether the error was from a cache or TCM access.
Figure 4-52 shows the CFLR bit assignments, when it indicates a correctable cache error.
Figure 4-52 CFLR - cache, bit assignments
Table 4-54 shows the CFLR bit assignments, when it indicates a correctable cache error.
Figure 4-53 shows the CFLR bit assignments, when it indicates a correctable TCM error.
Figure 4-53 CFLR - TCM, bit assignments
Side Reserved Type
31
30
29 26 25 24 23 14 13 5 4 2 1 0
Way Index
Reserved
Reserved
Table 4-54 CFLR - cache, bit assignments
Bits Name Function
[31:30] - RAZ
[29:26] Way Indicates the Way of the error.
[25:24] Side Indicates the source of the error. For cache errors, this value is always
0b00
.
[23:14] - RAZ
[13:5] Index Indicates the index of the location where the error occurred.
[4:2] - RAZ
[1:0] Type Indicates the type of access that caused the error:
0b00
= Instruction cache.
0b01
= Data cache.
Type
31 26 25 24 23
22
3210
Reserved Side
Address[22:3]
Reserved Reserved
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