System Control
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-77
ID073015 Non-Confidential
Table 4-55 shows the CFLR bit assignments, when it indicates a correctable TCM error.
To access the CFLR, read or write CP15 with:
MRC p15, 0, <Rd>, c15, c3, 0 : Read CFLR
MCR p15, 0, <Rd>, c15, c3, 0 : Write CFLR
4.3.31 Build Options Registers
These registers are implemented from the r1pn releases of the processor. Attempting to access
these registers in r0pn releases of the processor results in an Undefined Instruction exception.
c15, Build Options 1 Register
The Build Options 1 Register characteristics are:
Purpose Reflects the build configuration options used to build the processor.
Usage constraints The Build Options 1 Register is:
• a read-only register
• accessible in Privileged mode only
Configurations Available in all processor configurations.
Attributes See Table 4-56 on page 4-78.
Figure 4-54 shows the Build Options 1 Register bit assignments.
Figure 4-54 Build Options 1 Register bit assignments
Table 4-55 CFLR - TCM, bit assignments
Bits Name Function
[31:26] - RAZ
[25:24] Side Indicates the source of the error:
0b01
= ATCM
0b10
= BTCM
[23] - RAZ
[22:3] Address Indicates the address in the TCM where the error occurred.
[2] - RAZ
[1:0] Type Indicates the type of access that caused the error:
0b00
= Instruction.
0b01
= Data.
0b10
= AXI slave
0b11
is unused.
31 11 012
ReservedTCM_HI_INIT_ADDR
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