Debug
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-18
ID073015 Non-Confidential
MRC p14, 0, <Rd>, c0, c1, 0 ; Read Debug Status and Control Register
MCR p14, 0, <Rd>, c0, c1, 0 ; Write Debug Status and Control Register
DTR access mode
You can use the DTR access mode field to optimize data transfer between a debugger and the
processor.
The DTR access mode can be one of the following:
• Non-blocking. This is the default mode.
•Stall.
•Fast.
In Non-blocking mode, reads from DBGDTRTX and writes to DBGDTRRX and DBGITR are
ignored if the appropriate latched ready flag is not in the ready state. These latched flags are
updated on DBGDSCR reads. The following applies:
• writes to DBGDTRRX are ignored if DTRRXfull_l is set to b1
• reads from DBGDTRTX are ignored, and return an Unpredictable value, if DTRTXfull_l
is set to b0
• writes to DBGITR are ignored if InstrCompl_l is set to b0
• following a successful write to DBGDTRRX, DTRRXfull and DTRRXfull_l are set to b1
• following a successful read from DBGDTRTX, DTRTXfull and DTRTXfull_l are cleared
to b0
• following a successful write to DBGITR, InstrCompl and InstrCompl_l are cleared to b0.
Debuggers accessing these registers must first read DBGDSCR. This has the side-effect of
copying DTRRXfull and DTRTXfull to DTRRXfull_l and DTRTXfull_l. The debugger must
then:
• write to the DBGDTRRX if the DTRRXfull flag was b0 (DTRRXfull_l is b0)
• read from the DBGDTRTX if the DTRTXfull flag was b1 (DTRTXfull_l is b1)
• write to the DBGITR if the InstrCompl_l flag was b1.
However, debuggers can issue both actions together and later determine from the read
DBGDSCR value whether the operations were successful.
In Stall mode, the APB accesses to DBGDTRRX, DBGDTRTX, and DBGITR stall under the
following conditions:
• writes to DBGDTRRX are stalled until DTRRXfull is cleared
• writes to DBGITR are stalled until InstrCompl is set
• reads from DBGDTRTX are stalled until DTRTXfull is set.
Fast mode is similar to Stall mode except that in Fast mode, the processor fetches an instruction
from the DBGITR when a DBGDTRRX write or DBGDTRTX read succeeds. In Stall mode and
Nonblocking mode, the processor fetches an instruction from the DBGITR when an DBGITR
write succeeds.
12.4.6 Data Transfer Register
The DTR consists of two separate physical registers:
• the DBGDTRRX (Read Data Transfer Register)
• the DBGDTRTX (Write Data Transfer Register).
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