Debug
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-19
ID073015 Non-Confidential
The register accessed is dependent on the instruction used:
•writes,
MCR
and
LDC
instructions, access the DBGDTRTX
• reads,
MRC
and
STC
instructions, access the DBGDTRRX.
Read and write are used with respect to the processor.
For information on the use of these registers with the DTRTXfull flag and DTRRXfull flag, see
Debug communications channel on page 12-58. The Data Transfer Register, bits [31:0] contain
the data to be transferred.
Table 12-11 shows the DTR bit assignments.
12.4.7 Watchpoint Fault Address Register
The DBGWFAR Register characteristics are:
Purpose Holds the address of the instruction that triggers the watchpoint.
Usage constraints There are no usage constraints.
Configurations Available in all processor configurations.
Attributes See Table 12-12 on page 12-20.
Figure 12-6 shows the DBGWFAR bit assignments.
Figure 12-6 DBGWFAR Register bit assignments
Table 12-11 Data Transfer Register functions
Bits Name Function
[31:0] Data Reads the Data Transfer Register. This is read-only for the CP14 interface.
Reads of the DBGDTRRX through the coprocessor interface cause the DTRTXfull flag to be
cleared. However, reads of the DBGDTRRX through the APB port do not affect this flag.
[31:0] Data Writes the Data Transfer Register. This is write-only for the CP14 interface.
Writes to the DBGDTRTX through the coprocessor interface cause the DTRRXfull flag to be set.
However, writes to the DBGDTRTX through the APB port do not affect this flag.
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