FPU Programmers Model
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 11-8
ID073015 Non-Confidential
11.3.3 Floating-Point Exception Register, FPEXC
The FPEXC Register characteristics are:
Purpose Provides global enable and disable control of the VFP extension, and
indicate how the state of this extension is recorded.
Usage constraints • The FPEXC Register is accessible in Privileged modes only.
• Clearing EN disables VFP functionality, causing all VFP
instructions apart from privileged system register accesses to
generate an Undefined Instruction exception.
Configurations Use this register if the device is configured as a Cortex-R4F processor.
Attributes See Table 11-5.
Figure 11-4 shows the FPEXC bit assignments.
Figure 11-4 FPEXC Register bit assignments
Table 11-5 shows the FPEXC bit assignments.
11.3.4 Media and VFP Feature Registers, MVFR0 and MVFR1
The MVFR0 and MVFR1 Register characteristics are:
Purpose Describes the features supported by the FPU.
Usage constraints The MVFR0 and MVFR1 Registers:
• are read-only registers
• are accessible in Privileged modes only.
• ARM recommends that any software attempting to determine the
presence or absence of double-precision floating point hardware
support uses the MVFR1 register.
Configurations Use this register if the device is configured as a Cortex-R4F processor.
Attributes See Table 11-6 on page 11-9 and Table 11-7 on page 11-9.
Reserved
EN
Reserved
31 30 29 0
DEX
28
Table 11-5 FPEXC Register bit assignments
Bits Name Function
[31] - RAZ.
[30] EN VFP enable bit. Setting EN enables VFP functionality. Reset clears EN.
[29] DEX Set when an Undefined Instruction exception is taken because of a vector instruction that would
have been executed if the processor supported vectors. This field is cleared when an Undefined
Instruction exception is taken for any other reason. Resets to zero.
[28:0] - RAZ.
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