FPU Programmers Model
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 11-7
ID073015 Non-Confidential
Table 11-4 shows the FPSCR bit assignments.
Table 11-4 FPSCR Register bit assignments
Bits Name Function
[31] N Set if comparison produces a less than result, resets to zero
[30] Z Set if comparison produces an equal result, resets to zero
[29] C Set if comparison produces an equal, greater than, or unordered result, resets to zero
[28] V Set if comparison produces an unordered result, resets to zero
[27] QC Do Not Modify (DNM)/Read As Zero (RAZ)
[26] DNM DNM
[25] DN Default NaN mode enable bit:
0 = default NaN mode disabled, this is the reset value
1 = default NaN mode enabled.
[24] FZ Flush-to-zero mode enable bit:
0 = flush-to-zero mode disabled, this is the reset value
1 = flush-to-zero mode enabled.
[23:22] RMODE Rounding mode control field:
b00 = round to nearest (RN) mode, this is the reset value
b01 = round towards plus infinity (RP) mode
b10 = round towards minus infinity (RM) mode
b11 = round towards zero (RZ) mode.
[21:20] STRIDE Indicates the vector stride, the reset value is
0x0
[19] DNM DNM
[18:16] LEN Indicates the vector length, the reset value is
0x0
[15] IDE RAZ
[14:13] DNM DNM
[12] IXE RAZ
[11] UFE RAZ
[10] OFE RAZ
[9] DZE RAZ
[8] IOE RAZ
[7] IDC Input Subnormal cumulative flag, resets to zero
[6:5] DNM DNM
[4] IXC Inexact cumulative flag, resets to zero
[3] UFC Underflow cumulative flag, resets to zero
[2] OFC Overflow cumulative flag, resets to zero
[1] DZC Division by Zero cumulative flag, resets to zero
[0] IOC Invalid Operation cumulative flag, resets to zero
To Next Page
Loading...
