FPU Programmers Model
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 11-9
ID073015 Non-Confidential
Figure 11-5 shows the MVFR0 Register bit assignments.
Figure 11-5 MVFR0 Register bit assignments
Table 11-6 shows the MVFR0 Register bit assignments.
Figure 11-6 shows the MVFR1 Register bit assignments.
Figure 11-6 MVFR1 Register bit assignments
Table 11-7 shows the MVFR1 Register bit assignments.
RB
SVRM TE SPSR D DP
31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0
Table 11-6 MVFR0 Register bit assignments
Bits Name Function
[31:28] RM All VFP rounding modes supported:
0x1
[27:24] SV VFP short vector unsupported:
0x0
[23:20] SR VFP hardware square root supported:
0x1
[19:16] D VFP hardware divide supported:
0x1
[15:12] TE Only untrapped exception handling can be selected:
0x0
[11:8] DP Double precision supported in VFPv3:
0x2
[7:4] SP Single precision supported in VFPv3:
0x2
[3:0] RB 16x64-bit media register bank supported:
0x1
FZ
Reserved I DNSP LS
31 20 19 16 15 12 11 8 7 4 3 0
Table 11-7 MVFR1 Register bit assignments
Bits Name Function
[31:20] - Reserved
[19:16] SP Single-precision floating-point operations supported for VFP:
0b0000
= not supported
[15:12] I Integer operations supported for VFP:
0b0000
= not supported
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