ARM Cortex-R4 - Page 189

Level One Memory System
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 8-3
ID073015 Non-Confidential
Figure 8-1 L1 memory system block diagram
AXI master
Instruction cache
controller and
RAMs
Data cache
controller and
RAMs
B0TCM
AXI bus
AXI bus
External Tightly-Coupled Memory (TCM)
AXI slave
Data Processing Unit (DPU)
Memory
Protection Unit
(MPU)
Prefetch Unit
(PFU)
Load Store Unit
(LSU)
Interconnect
ATCM B1TCM
Processor