Level One Memory System
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 8-33
ID073015 Non-Confidential
; Clean entire data cache. This routine depends on the data cache size. It can be
omitted if it is known that the data cache has no dirty data (for example, if the cache
has not been enabled yet).
MRC p15, 0, r1, c1, c0, 1 ; Read ACTLR
; Change bits 5:3 as required
MCR p15, 0, r1, c1, c0, 1 ; Write ACTLR
MCR p15, 0, r0, c15, c5, 0 ; Invalidate entire data cache
MCR p15, 0, r0, c7, c5, 0 ; Invalidate entire instruction cache
MRC p15, 0, r0, c1, c0, 0 ; Read SCTLR
ORR r0, r0, #0x1 << 2 ; Enable data cache bit
ORR r0, r0, #0x1 << 12 ; Enable instruction cache bit
DSB
MCR p15, 0, r0, c1, c0, 0 ; Write SCTLR
ISB
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