Level One Memory System
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 8-37
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generates an event. See Table 6-1 on page 6-2 to see which events are CFLR-related. For
correctable cache errors, the CLFR does not record whether the error occurred in the data RAM
or tag/dirty RAM. This distinction is only made by the events.
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