Debug
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-51
ID073015 Non-Confidential
Synchronous Data abort
When a synchronous Data Abort occurs in debug state, the behavior of the
processor is as follows:
• PC, CPSR, SPSR_abt, and R14_abt are unchanged
• the processor remains in debug state
• DBGDSCR[6], sticky synchronous data abort bit, is set
• DFSR and DFAR are set to the same values as if the abort had occurred in
normal state.
Asynchronous Data Abort
When an asynchronous Data Abort occurs in debug state, the behavior of the
processor is as follows, regardless of the setting of the CPSR A bit:
• PC, CPSR, SPSR_abt, and R14_abt are unchanged
• the processor remains in debug state
• DBGDSCR[7], sticky asynchronous data abort bit, is set
• the asynchronous Data Abort does not cause the processor to perform an
exception entry sequence so DFSR remains unchanged
• the processor does not act on this asynchronous Data Abort on exit from the
debug state, that is, the asynchronous abort is discarded.
Asynchronous Data Aborts on entry and exit from debug state
On entering debug state, the processor executes a Data Synchronization Barrier (DSB)
sequence to ensure that any outstanding asynchronous Data Aborts are detected, before starting
debug operations.
If the DSB operation detects an asynchronous Data Abort, the processor records this event and
its type as if the CPSR A bit was set. The purpose of latching this event is to ensure that it can
be taken on exit from the debug state.
Before forcing the processor to leave debug state, the debugger must execute a DSB sequence
to ensure that all debugger-generated asynchronous Data Aborts are detected, and therefore
discarded, while still in debug state. After exiting debug state, the processor acts on any
previously recorded asynchronous Data Aborts if permitted by the CPSR A bit.
12.8.11 Leaving debug state
The debugger can force the processor to leave debug state:
• by setting the restart request bit, DBGDRCR[1], to 1
• through the Cross Trigger Interface (CTI) external restart request mechanism.
When one of those restart requests occurs, the processor:
1. Clears the DBGDSCR[1] core restarted flag.
2. Leaves debug state.
3. Clears the DBGDSCR[0] core halted flag.
4. Drives the DBGACK signal LOW, unless the DBGDSCR[11] DbgAck bit is set to 1.
5. Starts executing instructions from the address last written to the PC in the processor mode
and state indicated by the value of the CPSR. The CPSR IT execution state bit is restarted
with the value applying to the first instruction on restart.
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