Cycle Timings and Interlock Behavior
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. C-13
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Result Latency is one less if the result is used as the accumulate value for a subsequent multiply
accumulate. This only applies if the result is the same width as the accumulate value, that is 32
or 64 bits.
SMLALD
,
SMLALDX
1<Rn>, <Rm>- 2, 2
SMLSLD
,
SMLSLDX
1<Rn>, <Rm>- 2, 2
UMAAL
2<Rn>, <Rm>
<RdLo>, <RdHi>
3, 3
Table C-9 Example multiply instruction cycle timing behavior (continued)
Example
instruction
Cycles Early Reg Late Reg Result latency
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