ASIX AX99100 User Manual

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Copyright © 2016 ASIX Electronics Corporation. All rights reserved.
AX99100
PCIe to Multi I/O Controller
10
ALE Remap to A[10]
1: Re-assigned ALE pin to A[10], only valid when set bit7 to ‘0’
0: ALE pin is for ALE function
Hardware Default Value: 0x0
11
Reserved
12
CLKO Output Invert
1: Bus cycle active with rising edge
0: Bus cycle active with falling edge
Hardware Default Value: 0x0
13
Reserved
14
DREQ0 Wakeup Enable
1: Enable DREQ0 wakeup
0: Disable DREQ0 wakeup
Hardware Default Value: 0x0
15
DREQ1 Wakeup Enable
1: Enable DREQ1 wakeup
0: Disable DREQ1 wakeup
Hardware Default Value: 0x0
PCIe BAR0 Range (0x1B~0x1A)
Bit
Description
0
IO SPACE
1: Indicates Local Address Space 0 maps into I/O space.
0: Indicates Local Address Space 0 maps into Memory space.
Hardware Default Value: 0x0
2:1
Space Decode
When mapped into Memory space, the only valid value is 00. (32-bit access space with
non-prefetchable)
When mapped into I/O space, bit 1 should be ‘0’ and bit 2 will be loaded to BADDR0[2] to indicate the
decoding range.
Hardware Default Value: 0x0
3
Prefetchable
When mapped into Memory space, ‘1’ indicates reads are prefetchable.
When mapped into I/O space, this bit will be loaded to BADDR0[3] to indicate the decoding range.
Hardware Default Value: 0x0
15:4
BADDR0[15:4]
Specifies which Address bits to be used for decoding the PCIe access to Local Address Space 0. Each
bit corresponds to Address bit. ‘1’ is for PCI address decoding and ‘0’ means the occupied range for the
BAR0 access. The address bit 31 to 16 of BAR0 is always ‘1’.
Hardware Default Value: 0x000 (64KByte)

ASIX AX99100 Specifications

General

Brand	ASIX
Model	AX99100
Category	Controller
Language	English