ASIX AX99100 - Page 40

40
Copyright © 2016 ASIX Electronics Corporation. All rights reserved.
AX99100
PCIe to Multi I/O Controller
Local Address Space 1 Setting (0x2B~0x2A)
Bit
Description
0
INT1 Polarity
1: Active High
0: Active Low
Hardware Default Value: 0x0
1
INT1 Trigger Style
1: Level Trigger
0: Edge Trigger
Hardware Default Value: 0x0
2
DREQ1 Polarity
1: Active High
0: Active Low
Hardware Default Value: 0x0
3
DACK1 Polarity
1: Active High
0: Active Low
Hardware Default Value: 0x1
4
Local address Space 1 External Ready control
1: External RDY control usage for Local Address Space 1 bus access
0: Internal counter used for Local Address Space 1 bus access
Hardware Default Value: 0x0
5
Bus Endian and Alignment for Local Address Space 1
When data bus width is 16-bit,
1: Big endian
0: Little endian
When data bus width is 8-bit,
1: Data place to/from DA[15:8]
0: Data place to/from DA[7:0]
Hardware Default Value: 0x0
6
Data Bus Width for Local Address Space 1
1: Bus width 16-bit width
0: Bus width 8-bit width
Hardware Default Value: 0x1
7
ALE Insertion Enable for Local Address Space 1
1: Enable ALE insertion
0: Disable ALE insertion
Note: This bit should be set to ‘1’ when bit7 of “Local Bus Interrupt Enable/Miscellaneous Setting”,
offset 0x19~0x18, is ‘1’.
Hardware Default Value: 0x0
8
Chip Select (CS1n) Enable for Local address Space 1
1: Enable Local Address Space 1 Chip Select
0: Disable Local Address Space 1 Chip Select
Hardware Default Value: 0x1