ASIX AX99100 User Manual

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Copyright © 2016 ASIX Electronics Corporation. All rights reserved.
AX99100
PCIe to Multi I/O Controller
9
Local address Space 1 Enable
1: Enable the address mapping from PCIe BAR1 access to Local Address Space 1.
0: Disable the address mapping.
Hardware Default Value: 0x1
11:10
Reserved
Hardware Default Value: 0x3
12
Burst Read Enable for Local Address Space 1
1: Enable burst read access
0: Disable burst read access
Hardware Default Value: 0x1
14:13
Reserved
Hardware Default Value: 0x0
15
BAR1 Enable
1: Enable BAR1 access
0: Disable BAR1 access even offset 0x1D~0x1C, Local Bus PCIe BAR1 Range, are valid.
Hardware Default Value: 0x1
Local Address Space 1 Timing Setting (0x2F~0x2C)
Bit
Description
3:0
ALE Pulse Width (ALE_PW)
ALE pulse width cycle = (ALE_PW +1) * clock period
Hardware Default Value: 0x0
5:4
Data and Address Setup Time (DA_SET)
Address stable or ALE de-assert before RD_N or WR_N assert
Address setup time = DA_SET * clock period
Hardware Default Value: 0x0
7:6
Data and Address Hold Time (DA_HD)
Address and data de-assert after RD_N or WR_N de-assert
Address hold time = DA_HD * clock period
Hardware Default Value: 0x0
11:8
Read Access Time (RD_ACC)
For single access or burst read first cycle
Read access time = (RD_ACC + 1) * clock period
Hardware Default Value: 0x1
15:12
Burst Read Access Time (BRD_ACC)
For burst read second and late cycle
Burst read access time = (BRD_ACC + 1) * clock period
Note: BRD_ACC should large than 0x0.
Hardware Default Value: 0x1
19:16
Write Access Time (WR_ACC)
Write access time = (WR_ACC + 1) * clock period
Hardware Default Value: 0x0
23:20
Access GAP Time (AGAP)
Access back to back time = (AGAP + 1) * clock period
Hardware Default Value: 0x0

ASIX AX99100 Specifications

General

Brand	ASIX
Model	AX99100
Category	Controller
Language	English