ASIX AX99100 User Manual

39
Copyright © 2016 ASIX Electronics Corporation. All rights reserved.
AX99100
PCIe to Multi I/O Controller
Local Address Space 0 Timing Setting (0x25~0x22)
Bit
Description
3:0
ALE Pulse Width (ALE_PW)
ALE pulse width cycle = (ALE_PW +1) * clock period
Hardware Default Value: 0x0
5:4
Data and Address Setup Time (DA_SET)
Address stable or ALE de-assert before RD_N or WR_N assert
Address setup time = DA_SET * clock period
Hardware Default Value: 0x0
7:6
Data and Address Hold Time (DA_HD)
Address and data de-assert after RD_N or WR_N de-assert
Address hold time = DA_HD * clock period
Hardware Default Value: 0x0
11:8
Read Access Time (RD_ACC)
For single access or burst read first cycle
Read access time = (RD_ACC + 1) * clock period
Hardware Default Value: 0x1
15:12
Burst Read Access Time (BRD_ACC)
For burst read second and late cycle
Burst read access time = (BRD_ACC + 1) * clock period
Note: BRD_ACC should large than 0x0.
Hardware Default Value: 0x1
19:16
Write Access Time (WR_ACC)
Write access time = (WR_ACC + 1) * clock period
Hardware Default Value: 0x0
23:20
Access GAP Time (AGAP)
Access back to back time = (AGAP + 1) * clock period
Hardware Default Value: 0x0
27:24
CS0n Space Range
Local Address Space 0 Range for CS0n
CS0n Space Range = 2
(LCS0RAN + 1)
Hardware Default Value: 0xF
31:28
Reserved
Local Address Space 0 Address Setting (0x29~0x26)
Bit
Description
15:0
Local Address Space 0 address shift Base
Hardware Default Value: 0x0000
31:16
CS0n space Starting Address
Starting Address Shift of CS0n for Local Address Space 0
Hardware Default Value: 0x0000

ASIX AX99100 Specifications

General

Brand	ASIX
Model	AX99100
Category	Controller
Language	English