ASIX AX99100 User Manual

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Copyright © 2016 ASIX Electronics Corporation. All rights reserved.
AX99100
PCIe to Multi I/O Controller
5
Bus Endian and Alignment for Local Address Space 0
When data bus width is 16-bit,
1: Big endian
0: Little endian
When data bus width is 8-bit,
1: Data place to/from DA[15:8]
0: Data place to/from DA[7:0]
Hardware Default Value: 0x0
6
Data Bus Width for Local Address Space 0
1: Bus width 16-bit width
0: Bus width 8-bit width
Hardware Default Value: 0x1
7
ALE Insertion Enable for Local Address Space 0
1: Enable ALE insertion
0: Disable ALE insertion
Note: This bit should be set to ‘1’ when bit7 of “Local Bus Interrupt Enable/Miscellaneous Setting”,
offset 0x19~0x18, is ‘1’.
Hardware Default Value: 0x0
8
Chip Select (CS0n) Enable for Local address Space 0
1: Enable Local Address Space 0 Chip Select
0: Disable Local Address Space 0 Chip Select
Hardware Default Value: 0x1
9
Local address Space 0 Enable
1: Enable the address mapping from PCIe BAR0 access to Local Address Space 0.
0: Disable the address mapping.
Hardware Default Value: 0x1
11:10
Reserved
Hardware Default Value: 0x3
12
Burst Read Enable for Local Address Space 0
1: Enable burst read access
0: Disable burst read access
Hardware Default Value: 0x1
14:13
Reserved
Hardware Default Value: 0x0
15
BAR0 Enable
1: Enable BAR0 access
0: Disable BAR0 access even offset 0x1B~0x1A, Local Bus PCIe BAR0 Range, are valid.
Hardware Default Value: 0x1

ASIX AX99100 Specifications

General

Brand	ASIX
Model	AX99100
Category	Controller
Language	English