Compaq Evo D500 - Page 8

Technical Reference Guide
CHAPTER 4 SYSTEM SUPPORT ..............................................................................................................
4.1 INTRODUCTION....................................................................................................................... 4-1
4.2 PCI BUS OVERVIEW................................................................................................................ 4-2
4.2.1 PCI BUS TRANSACTIONS............................................................................................... 4-3
4.2.2 PCI BUS MASTER ARBITRATION ................................................................................. 4-6
4.2.3 OPTION ROM MAPPING ................................................................................................. 4-7
4.2.4 PCI INTERRUPTS.............................................................................................................. 4-7
4.2.5 PCI POWER MANAGEMENT SUPPORT........................................................................ 4-7
4.2.6 PCI SUB-BUSSES .............................................................................................................. 4-7
4.2.7 PCI CONFIGURATION ..................................................................................................... 4-8
4.2.8 PCI CONNECTOR .............................................................................................................4-9
4.3 AGP BUS OVERVIEW ............................................................................................................ 4-10
4.3.1 BUS TRANSACTIONS.................................................................................................... 4-10
4.3.2 AGP CONFIGURATION ................................................................................................. 4-13
4.3.3 AGP CONNECTOR.......................................................................................................... 4-14
4.4 SYSTEM RESOURCES ........................................................................................................... 4-15
4.4.1 INTERRUPTS................................................................................................................... 4-15
4.4.2 DIRECT MEMORY ACCESS.......................................................................................... 4-19
4.5 SYSTEM CLOCK DISTRIBUTION........................................................................................ 4-22
4.6 REAL-TIME CLOCK AND CONFIGURATION MEMORY................................................. 4-23
4.6.1 CLEARING CMOS........................................................................................................... 4-23
4.6.2 CMOS ARCHIVE AND RESTORE................................................................................. 4-24
4.6.3 STANDARD CMOS LOCATIONS ................................................................................. 4-24
4.7 SYSTEM MANAGEMENT ..................................................................................................... 4-33
4.7.1 SECURITY FUNCTIONS ................................................................................................ 4-33
4.7.2 POWER MANAGEMENT ............................................................................................... 4-35
4.7.3 SYSTEM STATUS ........................................................................................................... 4-35
4.7.4 THERMAL SENSING AND COOLING ......................................................................... 4-36
4.8 REGISTER MAP AND MISCELLANEOUS FUNCTIONS ................................................... 4-38
4.8.1 SYSTEM I/O MAP ........................................................................................................... 4-38
4.8.2 82801 ICH2 GENERAL PURPOSE FUNCTIONS.......................................................... 4-39
4.8.3 LPC47B357 I/O CONTROLLER FUNCTIONS .............................................................. 4-40
CHAPTER 5 INPUT/OUTPUT INTERFACES..........................................................................................
5.1 INTRODUCTION....................................................................................................................... 5-1
5.2 ENHANCED IDE INTERFACE ................................................................................................ 5-1
5.2.1 IDE PROGRAMMING ....................................................................................................... 5-1
5.2.2 IDE CONNECTOR .............................................................................................................5-3
5.3 DISKETTE DRIVE INTERFACE.............................................................................................. 5-4
5.3.1 DISKETTE DRIVE PROGRAMMING.............................................................................. 5-5
5.3.2 DISKETTE DRIVE CONNECTOR ................................................................................... 5-7
5.4 SERIAL INTERFACE ................................................................................................................ 5-8
5.4.1 RS-232 INTERFACE..........................................................................................................5-8
5.4.2 COM1 PORT HEADER...................................................................................................... 5-9
5.4.3 SERIAL INTERFACE PROGRAMMING......................................................................... 5-9
5.5 PARALLEL INTERFACE........................................................................................................ 5-11
5.5.1 STANDARD PARALLEL PORT MODE ........................................................................ 5-11
5.5.2 ENHANCED PARALLEL PORT MODE........................................................................ 5-12
Compaq Deskpro and Evo Personal Computers
Featuring Intel Celeron and Pentium III Processors
Fifth Edition –- March 2002
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