Dell EMC PowerEdge XR2 - Page 36

Option Description
Maximum data rate indicates that the BIOS runs the communication links at the maximum frequency supported by
the processors. You can also select specic frequencies that the processors support, which can vary.
For best performance, you should select Maximum data rate. Any reduction in the communication link frequency
aects the performance of non-local memory accesses and cache coherency trac. In addition, it can slow access
to non-local I/O devices from a particular CPU.
However, if power saving considerations outweigh performance, you might want to reduce the frequency of the
CPU communication links. If you do this, you should localize memory and I/O accesses to the nearest NUMA node
to minimize the impact to system performance.
Virtualization
Technology
Enables or disables the virtualization technology for the processor. This option is set to Enabled by default.
Adjacent Cache
Line Prefetch
Optimizes the system for applications that need high utilization of sequential memory access. This option is set to
Enabled by default. You can disable this option for applications that need high utilization of random memory
access.
Hardware
Prefetcher
Enables or disables the hardware prefetcher. This option is set to Enabled by default.
DCU Streamer
Prefetcher
Enables or disables the Data Cache Unit (DCU) streamer prefetcher. This option is set to Enabled by default.
DCU IP Prefetcher Enables or disables the Data Cache Unit (DCU) IP prefetcher. This option is set to Enabled by default.
Sub NUMA Cluster Enables or disables the Sub NUMA Cluster. This option is set to EnabledDisabled by default.
Enables or disables the Sub NUMA Cluster. This option is set to Disabled by default.
UPI Prefetch Enables you to get the memory read started early on DDR bus. The Ultra Path Interconnect (UPI) Rx path will
spawn the speculative memory read to Integrated Memory Controller (iMC) directly. This option is set to Enabled
by default.
Logical Processor
Idling
Enables you to improve the energy eciency of a system. It uses the operating system core parking algorithm and
parks some of the logical processors in the system which in turn allows the corresponding processor cores to
transition into a lower power idle state. This option can only be enabled if the operating system supports it. It is set
to Disabled by default.
Congurable TDP Enables you to recongure the processor Thermal Design Power (TDP) levels during POST based on the power
and thermal delivery capabilities of the system. TDP veries the maximum heat the cooling system is needed to
dissipate. This option is set to Nominal by default.
NOTE: This option is only available on certain stock keeping units (SKUs) of the processors.
x2APIC Mode Enables or disables the x2APIC mode. This option is set to Disabled by default.
Number of Cores
per Processor
Controls the number of enabled cores in each processor. This option is set to All by default.
Processor 64-bit
Support
Species if the processors support 64-bit extensions.
Processor Core
Speed
Species the maximum core frequency of the processor.
Process Bus Speed Displays the bus speed of the processor.
Processor n
NOTE: Depending on the number of CPUs, there might be up to n processors listed.
The following settings are displayed for each processor installed in the system:
36 Pre-operating system management applications