DIGITAL-LOGIC AG PCCP5 Manual V2.3
82
#define VIC3_Y_FLIPPED 0x02 // capture direction, 1:bottom to top,
// 0: top to bottom
#define VIC3_HFILTER 0x04 // 1:enable horizontal filter at input,
// 0:no h filter
#define VIC3_DB_VLOCK 0x08 // 1:DoubleBuffer Vsync locked,
// 0:DoubleBuffer CPU forced
#define VIC3_ENABLE_DB 0x10 // 1:Enable DoubleBuffer,
// 0:No DoubleBuffer
#define VIC3_PTR1_INUSE 0x20 // 1:PTR 1 in use for DoubleBuffer,
// 0:PTR 0 in use for DoubleBuffer
#define VIC3_CAPTURE_NF 0x80 // 1:Capture Nth Frame/Field,
// 0:Capture single frame
//-------------------------------------------------------------------------
// Bit definition of Video Input Status Register (MR_VIN_CTRL_4)
//-------------------------------------------------------------------------
#define VIC4_FRM_READY 0x01 // 1:Frame is ready for grab by CPU
// (synced with VSync)
#define VIC4_VSYNC 0x08 // VSync after polarity correction
// (read only)
#define VIC4_PQE_PIXEL 0x10 // 1:Pixel Qualifier as valid pixel
// 0:Pixel Qualifier as Blank signal
#define VIC4_PQP_INV 0x20 // 1:Pixel Qualifier polarity inverted,
// 0:Pixel Qualifier normal
#define VIC4_SWAP_UV 0x40 // 1:Swap U & V,
// 0:UV Normal sequence
#define VIC4_HY_LUV 0x80 // 1:Y on high and UV on low pins(VESA)
// 0:UV on high and Y on low pins
//-------------------------------------------------------------------------
// Bit definition of Video Display Control Register1 (MR_VDP_CTRL_1)
//-------------------------------------------------------------------------
#define VDC1_X_MIRRORED 0x01 // 1:mirrored (right to left),
// 0:normal (left to right)
#define VDC1_Y_FLIPPED 0x02 // 1:Flipped (bottom to top),
// 0:normal (top to bottom)
#define VDC1_ZOOM_X 0x04 // 1:enable x_zoom (zoom based on reg),
// 0:normal
#define VDC1_ZOOM_Y 0x08 // 1:enable y_zoom (zoom based on reg),
// 0:normal
#define VDC1_INTERLACE 0x10 // 1:VGA Mode is interlaced,
// 0:non-interlaced mode
//-------------------------------------------------------------------------
// Bit definition of Video Display Control Register2 (MR_VDP_CTRL_2)
//-------------------------------------------------------------------------
#define VDC2_YUV422 0x00 // Video Buf is YUV4:2:2
#define VDC2_UV_SWAP 0x01 // Video Buf is YUV4:2:2 with UV Swap
#define VDC2_SIGNED_UV 0x02 // Video Buf is YUV4:2:2 with Signed UV
#define VDC2_YUV422_UVS 0x01 // Video Buf is YUV4:2:2 with UV Swap
#define VDC2_YUV422_SUV 0x02 // Video Buf is YUV4:2:2 with Signed UV
#define VDC2_YUV422_UV 0x03 // Video Buf is YUV4:2:2 Signed UV&Sawp
#define VDC2_RGB555 0x09 // Video Buffer is RGB15 (5-5-5)
#define VDC2_RGB565 0x08 // Video Buffer is RGB16 (5-6-5)
#define VDC2_FORMAT 0x1F // All format bits
#define VDC2_H_INTERPOL 0x20 // Enable Horizontal Interpolation
#define VDC2_VI_RUNAVRG 0x40 // Vertical Interpolation is done as
// running average method
#define VDC2_V_INTERPOL 0x80 // Enable Vertical Interpolation
//-------------------------------------------------------------------------
// Bit definition of Video Display Control Register3 (MR_VDP_CTRL_3)
//-------------------------------------------------------------------------
#define VDC3_DB_TRIGGER 0x08 // Display new pointer on next VSync
To Next Page
Loading...
