DIGITAL-LOGIC MICROSPACE PCC-P5 - Page 83

DIGITAL-LOGIC AG PCCP5 Manual V2.3
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#define VDC3_DB_CPU_PTR 0x04 // 1:Dbl buf src is buf ptr set by CPU
// 0:Dbl buf src is Input Aqisition's
// last frame
#define VDC3_DB_PTR2 0x10 // 1:CPU buffer is pointer 2
// 0:CPU buffer is pointer 1
#define VDC3_DB_VLOVK 0x20 // 1:Double buffer is VSync locked
// 0:Double buffer is unlocked
//-------------------------------------------------------------------------
// Bit definition of Video Display Status Register4 (MR_VDP_CTRL_4)
//-------------------------------------------------------------------------
#define VDC4_DB_PENDING 0x01 // 1:hasn't displayed CPU set buffer
// 0:CPU Set buffer is displayed or in
// process of being displayed
#define VDC4_DB_USEPTR2 0x02 // 1:PTR2 is being displayed
// 0:PTR1 is being displayed
//-------------------------------------------------------------------------
// Bit definition of Video Color Key Control Register (MR_VDP_CKEY_CTRL)
//-------------------------------------------------------------------------
#define VDC_EV_OVERLAY 0x01 // 1:Enable video overlay
// 0:Display graphics only
#define VDC_EV_COLOR_KEY 0x02 // 1:Enable video display using clr key
// 0:Color Key Disabled
#define VDC_EV_XY_RECT 0x04 // 1:Enable video display in Rect Rgn
// 0:Video Display in Rect Rgn disabled
#define VDC_ENABLE_VAFC 0x08 // 1:Enable external VAFC (like 545)
// for color key only
// 0:Our own video play back
#define VDC_VAFC_18 0x10 // 1:18 bit external VAFC
// 0:16 bit external VAFC
#define VDC_BIT_15_KEY 0x40 // 1:in 16BPP modes MSB is routed thru
// Blue0 for color key
// 0:normal color key
#define VDC_BIT_0_KEY 0x80 // 1:enable blue0 clr key for 16/24BP
// 0:normal color key for 16/24BPP mode
#define VIN_SCALE_X_MAX 0x100 // max value of x_scale reg (8 bit reg)
#define VIN_SCALE_Y_MAX 0x100 // max value of y_scale reg (8 bit reg)
//#define VDP_ZOOM_X_MAX 0x100 // max value of x_zoom reg (ES1 100h)
//#define VDP_ZOOM_Y_MAX 0x100 // max value of y_zoom reg (ES1 100h)
#define VDP_ZOOM_X_MAX 0x40 // max value of x_zoom reg (ES0 40h)
#define VDP_ZOOM_Y_MAX 0x40 // max value of y_zoom reg (ES0 40h)
/*