Enclustra Mars ZX3 - User I;O; Pinout; Module Connector Types; User I;Os

Height Type Description Max component height under the module
4.0 mm TE 292406-4 DDR2-SODIMM, 1.8 V 0 mm
5.2 mm TE 1565917-4 DDR2-SODIMM, 1.8 V 1 mm
6.5 mm TE 5-1746530-4 DDR2-SODIMM, 1.8 V 2 mm
8.0 mm TE 1827341-4 DDR2-SODIMM, 1.8 V 4 mm
Table 4: Module Connector Types
2.9 User I/O
2.9.1 Pinout
Information on the Mars ZX3 SoC module pinout can be found in the Enclustra Mars Master Pinout [11], and
in the additional document Enclustra Module Pin Connection Guidelines [10].
The naming convention for the user I/Os is:
IO_B<BANK>_L<PAIR><_SPECIAL_FUNCTION>_<PACKAGE_PIN>_<POLARITY>.
For example, IO_B35_L1_AD0_F16_P is located on pin F16 of I/O bank 35, pair 1, it is an XADC auxiliary analog
input capable pin and it has positive polarity, when used in a differential pair.
For the signal lines shared between Programmable Logic (PL) and Processing System (PS), the naming con-
vention is:
IO_<MIO_PIN>_B<BANK>_L<PAIR>_<PACKAGE_PIN>
For example, IO_MIO44_B33_L16_U17 is connected to FPGA pin U17 and in parallel to the PS MIO pin 44.
Please note that for the shared pins only one of the driving pins (FPGA pin, MIO pin) may be active.
The multi-region clock capable pins are marked with “MRCC”, while the single region clock capable pins are
marked with “SRCC” in the signal name. For details on their function and usage, please refer to the Xilinx
documentation.
Table 5 includes information related to the total number of I/Os available in each I/O bank and possible
limitations.
Signal Name Signals Pairs Differential Single-ended I/O Bank
IO_<MIO_PIN>_B33_<...> 12 6 In/Out In/Out 33
IO_B34_<...> 48 24 In/Out In/Out 34
IO_B35_<...> 48 24 In/Out In/Out 35
Total 108 54 - - -
Table 5: User I/Os
Please note that for the 7 Series FPGAs there are restrictions on the VCCO voltage when using LVDS I/Os;
refer to Xilinx AR# 43989 for details.
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