2.12 Reset
The power-on reset signal (POR) and the PS system reset signal (SRST) of the SoC device are available on
the module connector.
Pulling PS_POR# low resets the SoC device, the Ethernet and the USB PHYs, and the flash devices. Please
refer to the Enclustra Module Pin Connection Guidelines [10] for general rules regarding the connection of
reset pins.
Pulling PS_SRST# low resets the SoC device. For details on the functions of the PS_POR_B and PS_SRST_B
signals refer to the Zynq-7000 Technical Reference Manual [18].
Table 17 presents the available reset signals. Both signals, PS_POR# and PS_SRST#, have on-board 10 kΩ
pull-up resistors to VCC_CFG_PS_B13_B33.
Signal Name Connector Pin Package Pin FPGA Pin Type Description
PS_POR# 196 B5 PS_POR_B Power-on reset
PS_SRST# 192 C9 PS_SRST_B System reset
Table 17: Reset Resources
Please note that PS_POR# is automatically asserted if PWR_GOOD is low.
2.13 LEDs
The four LEDs on the Mars ZX3 SoC module are connected to the FPGA logic, and they are active-low.
Signal Name FPGA Pin Remarks
LED0# H18 User function/active-low
LED1# AA14 User function/active-low; shared with MIO15
LED2# AA13 User function/active-low
LED3# AB15 User function/active-low
Table 18: LEDs
LED1# is shared between the PL (pin AA14) and PS (MIO15); for a correct status signaling the LED signal
should be only driven from one side (PL or PS) low (for LED on) or set to high impedance (for LED off). Note
that MIO15 is a dual-function pin and by changing the value of this signal, the MDIO/I2C selection circuit is
also affected - please refer to Section 2.9.7 for details on the usage of this pin.
2.14 DDR3 SDRAM
There is a single DDR3 SDRAM channel on the Mars ZX3 SoC module attached directly to the PS side and
is available only as a shared resource to the PL side.
The DDR3 SDRAM is operated at 1.35 V (low power mode) or at 1.5 V, depending on a selection signal. Two
16-bit memory chips are used to build a 32-bit wide memory.
The maximum memory bandwidth on the Mars ZX3 SoC module is:
1066 Mbit/sec × 32 bit = 4264 MB/sec
D-0000-424-004 24 / 48 Version 05, 21.08.2018
To Next Page
Loading...
