2.9.2 Differential I/Os
When using differential pairs, a differential impedance of 100 Ω must be matched on the base board, and
the two nets of a differential pair must have the same length.
The information regarding the length of the signal lines from the SoC device to the module connector is
available in Mars ZX3 SoC Module IO Net Length Excel Sheet [3]. This enables the user to match the total
length of the differential pairs on the base board if required by the application.
2.9.3 I/O Banks
Table 6 describes the main attributes of the FPGA and PS I/O banks, and indicates which peripherals are
connected to each I/O bank. All I/O pins within a particular I/O bank must use the same I/O (VCC_IO) and
reference (VREF) voltages.
Bank Connectivity VCC_IO VREF
Bank 0 Configuration
User selectable
-
VCC_CFG_PS_B13_B33
Bank 13
Ethernet PHY User selectable
-
Most pins shared with MIO 16-27 VCC_CFG_PS_B13_B33
Bank 33
Module connector User selectable
-
Most pins shared with MIO 40-51 VCC_CFG_PS_B13_B33
Bank 34 Module connector
User selectable IO_B34_L6_VREF_M16_N
VCC_IO_B34 IO_B34_L19_VREF_P15_N
Bank 35 Module connector
User selectable IO_B35_L6_VREF_F17_N
VCC_IO_B35 IO_B35_L19_VREF_H20_N
PS MIO0 QSPI and NAND flash
User selectable
1
-
VCC_CFG_PS_B13_B33
PS MIO1
Ethernet PHY, USB PHY, User selectable
0.9 V
Module connector VCC_CFG_PS_B13_B33
2
PS DDR DDR3 SDRAM
User selectable
3
0.5 × VREF_DDR3L
VCC_DDR3L
Table 6: I/O Banks
2 3
1
For modules of revision 4 or older, the MIO0 bank voltage is tied to 3.3 V.
2
On modules of revision 4 or older, the name of this voltage supply signal is: VCC_CFG_MIO1_B13_B33.
3
The DDR3 SDRAM supports voltages of 1.5 or 1.35 V. Please refer to Section 2.14 for details.
D-0000-424-004 16 / 48 Version 05, 21.08.2018
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