Enclustra Mars ZX3 - JTAG Boot Mode; NAND Flash Boot Mode; Jtag; Boot Mode Resistor - Assembly Drawing Top View

3.3.1 JTAG Boot Mode
For JTAG boot mode selection, the following steps must be followed:
• BOOT_MODE must be set to logic low
• MIO5 (NAND_IO0/FLASH_IO3) must be pulled to GND (refer to Table 34 for details)
Module Hardware changes required to pull MIO5 to GND
MA-ZX3 - R1 R111 must be mounted
MA-ZX3 - R2 and R3 R111 must be short-circuited
MA-ZX3 - R4 and newer R213 must be short-circuited
Table 34: Hardware Changes for JTAG and NAND Boot Modes
Figure 11: Boot Mode Resistor - Assembly Drawing Top View (Refer to Section 2.5 for the latest Assembly Drawing)
3.3.2 NAND Flash Boot Mode
For NAND flash boot mode selection, the following steps must be followed:
• BOOT_MODE must be set to logic high
• MIO5 (NAND_IO0/FLASH_IO3) must be pulled to GND (refer to Table 34 for details)
In the NAND boot mode, the PS boots from the NAND flash located on the module. The flash device is
connected to the PS MIO pins 0 and 2-14.
In order to boot from the NAND flash, the user must enable the NAND controller in the Vivado block design
and set the timing parameters as described in Section 2.16.3. After these changes, a new FSBL must be
generated and used for the Zynq boot image creation.
3.4 JTAG
The FPGA and the PS JTAG interfaces are connected into one single chain available on the module connector.
The SoC device, the QSPI flash, and the NAND flash can be configured via JTAG from Xilinx SDK or Xilinx
Vivado Hardware Manager.
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