2.18.5 PHY Configuration
The configuration of the Ethernet PHY is bootstrapped when the PHY is released from reset. Make sure all
I/Os on the RGMII interface are initialized and all pull-up or pull-down resistors are disabled at that moment.
The bootstrap options of the Ethernet PHY are set as indicated in Table 27.
Please note that the RGMII delays in the Ethernet PHY need to be configured before the Ethernet interface
can be used. This is done in the source files within the First Stage Boot Loader (FSBL) application provided
in the Mars ZX3 SoC module reference design [2].
Pin Signal Value Description
MODE[3-0] 1110 RGMII mode: advertise all capabilities (10/100/1000, half/full duplex) ex-
cept 1000Base-T half duplex.
PHYAD[2-0] 011 MDIO address 3
Clk125_EN 0 125 MHz clock output disabled
LED_MODE 1 Single LED mode
LED1/LED2 1 Active-low LEDs
Table 27: Gigabit Ethernet PHY Configuration
For the Ethernet PHY configuration via the MDIO interface, the MDC clock frequency must not exceed 1
MHz.
2.19 USB 2.0
The Mars ZX3 SoC module has an on-board USB 2.0 PHY connected to the SoC device. The USB interface
can be configured for USB host, USB device and USB On-The-Go (host and device capable) operations.
2.19.1 USB PHY Type
Table 28 describes the equipped USB PHY device type on the Mars ZX3 SoC module.
PHY Type Manufacturer Type
USB3320C Microchip USB 2.0 PHY
Table 28: USB 2.0 PHY Type
2.19.2 Signal Description
The ULPI interface is connected to MIO pins 28-39 for use with the integrated USB controller.
2.20 Real-Time Clock (RTC)
A real-time clock is connected to the I2C bus. The RTC features a battery-buffered 128 bytes user SRAM and
a temperature sensor. See Section 4 for details on the I2C bus on the Mars ZX3 SoC module.
VBAT pin of the RTC is connected to VCC_BAT on the module connector, and can be connected directly to
a 3 V battery. Please refer to the Enclustra Module Pin Connection Guidelines [10] for details.
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