Enclustra Mars ZX3 - Signal Description; External Connectivity; MDIO Address; Gigabit Ethernet Signal Description

2.18.2 Signal Description
The RGMII interface is connected to MIO pins 16-27 for use with the hard macro MAC, and in parallel to PL
bank 13 pins for use with the FPGA logic. The interrupt output of the Ethernet PHY is connected to the I2C
interrupt line, available on an EMIO pin.
The Gigabit Ethernet connections are presented in Table 26. All listed pins are operated at
VCC_CFG_PS_B13_B33 I/O voltage.
Signal Name MIO Pin PL Pin
ETH_RST# - AB11
I2C_INT# - H17
ETH_MDC MIO52
10
AA12
ETH_MDIO MIO53
10
AB12
ETH_RXC MIO22 Y9
ETH_RX_CTL MIO27 Y8
ETH_RXD0 MIO23 U10
ETH_RXD1 MIO24 Y11
ETH_RXD2 MIO25 W11
ETH_RXD3 MIO26 U11
ETH_TXC MIO16 W10
ETH_TX_CTL MIO21 V10
ETH_TXD0 MIO17 V8
ETH_TXD1 MIO18 W8
ETH_TXD2 MIO19 U6
ETH_TXD3 MIO20 V9
Table 26: Gigabit Ethernet Signal Description
2.18.3 External Connectivity
The Ethernet signal lines can be connected directly to the magnetics. Please refer to the Enclustra Module
Pin Connection Guidelines [10] for details regarding the connection of Ethernet signals.
2.18.4 MDIO Address
The MDIO address assigned to the Gigabit Ethernet PHY is 3.
The MDIO interface is connected by default to MIO pins 52-53. These pins can also be used to access the
I2C bus - for details, please refer to Section 2.9.7.
10
MIO52 and MIO53 can be used for either MDIO or I2C. Please refer to Section 2.9.7 for details.
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