Enclustra Mars ZX3 - DDR3 Low Voltage Operation; QSPI Flash; DDR3 SDRAM Parameters; DDR3 Board Timing

Parameter Value
Memory type DDR3/DDR3L
DRAM bus width 32 bit
Operating frequency 400-533 MHz
DRAM chip bus width 16 bit
DRAM chip capacity 2048-4096 Mbits
Speed bin DDR3_1066F/DDR3L_1066F
Bank bits 3
Row bits 14-15 (depending on the module type)
Column bits 10
CAS latency 7
CAS write latency 6
RAS to CAS delay 7
Precharge time 7
tRC 50.625 ns
tRASmin 37.5 ns
tFAW 40.0 ns
Table 20: DDR3 SDRAM Parameters
Parameter Byte 3 Byte 2 Byte 1 Byte 0
DQS to clock delay (ns) 0.0 0.0 0.012 0.0
Board delay (ns) 0.285 0.248 0.241 0.238
Table 21: DDR3 Board Timing
2.14.5 DDR3 Low Voltage Operation
The default voltage of the DDR3 is 1.5 V. In order to enable low voltage mode (1.35 V), DDR3_VSEL (pin AA22)
must be driven logic 0, and DDR3L memory type must be selected in the PS configuration parameters in
Vivado.
For 1.5 V operation, DDR3_VSEL must be set to high impedance (not driven logic 1).
2.15 QSPI Flash
The QSPI flash can be used to boot the PS, and to store the FPGA bitstream, ARM application code and
other user data.
D-0000-424-004 26 / 48 Version 05, 21.08.2018