Warning!
All configuration signals except for BOOT_MODE must be high impedance as soon as the device is
released from reset. Violating this rule may damage the equipped SoC device, as well as other devices
on the Mars ZX3 SoC module.
3.2 Pull-Up During Configuration
Figure 10 illustrates the configuration of the I/O signals during power-up.
Figure 10: Pull-Up During Configuration (PUDC)
The Pull-Up During Configuration signal (PUDC) is configured using a multiplexer to low state during FPGA
configuration, and to high impedance after this process is done.
If the user does not drive a high value on this signal during configuration, then the PUDC signal will be
pulled to GND via a 1 kΩ resistor. As PUDC is an active-low signal, all FPGA I/Os will have the internal pull-up
resistors enabled during device configuration.
If the application requires that all FPGA I/Os have the internal pull-up resistors disabled during device con-
figuration, the user must attach to the module connector a driver capable to pull IO_B34_L3_PUDC#_K16_P
signal high.
For details on the PUDC signal please refer to the Zynq-7000 All Programmable SoC Technical Reference
Manual [18].
3.3 Boot Mode
The boot mode can be selected via a signal available on the module connector.
Table 33 describes the available boot modes on the Mars ZX3 SoC module.
BOOT_MODE Description
0 Boot from QSPI flash
1 Boot from SD card
Table 33: Boot Modes
Additionally, JTAG and NAND flash boot modes are available. These are further presented in Sections 3.3.1
and 3.3.2.
11
The CFGBVS_0 pin is set automatically to GND (if VCC_CFG_PS_B13_B33 is less than or equal to 1.8 V) or to VCCO (if
VCC_CFG_PS_B13_B33 is 2.5 V or 3.3 V).
D-0000-424-004 34 / 48 Version 05, 21.08.2018
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