3 Device Configuration
3.1 Configuration Signals
The PS of the SoC needs to be configured before the FPGA logic can be used. Xilinx Zynq devices need
special boot images to boot from QSPI flash or SD card. For more information, please refer to the Xilinx
Zynq-7000: Concepts, Tools, and Techniques document [20].
Table 32 describes the most important configuration pins and their location on the module connector. These
signals allow the SoC to boot from QSPI flash or SD card, and can be used to program the QSPI flash from
an external master. Please refer to Section 3.8 for details.
Signal SoC Mod. Conn. Comments
Name Pin Type Pin Description
FLASH_CLK/NAND_IO1 MIO6 182 SPI CLK 20 kΩ pull-down
FLASH_DO/NAND_WE# MIO3 184 SPI MISO 20 kΩ pull-down
FLASH_DI/NAND_ALE MIO2 186 SPI MOSI 20 kΩ pull-down
FLASH_CS# MIO1 188 SPI CS#
10 kΩ pull-up to
VCC_CFG_PS_B13_B33
FPGA_DONE DONE_0 194
FPGA configuration 1 kΩ pull-up to
done VCC_CFG_PS_B13_B33
FPGA_CFGBVS CFGBVS_0 -
Configuration bank 10 kΩ pull-up to
voltage select
11
VCC_CFG_PS_B13_B33
PS_POR# PS_POR_B 196
Must be pulled to
GND for a short pe-
riod before QSPI flash
programming.
10 kΩ pull-up to
PS_SRST# must be low
when PS_POR# is re-
leased.
VCC_CFG_PS_B13_B33
PS_SRST# PS_SRST_B 192
Must be pulled to
GND during QSPI
flash programming.
10 kΩ pull-up to
When released, all
other pins of the SPI
interface must be high
impedance.
VCC_CFG_PS_B13_B33
BOOT_MODE - 190 Boot mode selection
10 kΩ pull-up to
VCC_CFG_PS_B13_B33
Table 32: SoC Configuration Pins
D-0000-424-004 33 / 48 Version 05, 21.08.2018
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