connection.
The GTR pairs support data rates of 6 Gbit/sec and can be used for the implementation of several interfaces
such as PCIe Gen2 ×4, USB 3.0, DisplayPort, SATA, or Ethernet SGMII. Please refer to the Zynq UltraScale+
MPSoC Technical Reference Manual [19] and to the Zynq UltraScale+ MPSoC Overview [23] for details.
A 100 MHz LVDS oscillator and a 27 MHz CMOS oscillator provide reference clock inputs to the PS GTR bank
505. Please refer to Section 2.12 for details.
Warning!
The maximum data rate on the MGT lines on the Mercury+ XU1 SoC module depends on the routing
path for these signals. Adequate signal integrity over the full signal path must be ensured when using
MGTs at high performance rates.
Warning!
No AC coupling capacitors are placed on the Mercury+ XU1 SoC module on the MGT lines - make sure
capacitors are mounted, if required, on the base board (close to the module pins), to prevent MGT lines
from being damaged.
2.11 Power
2.11.1 Power Generation Overview
The Mercury+ XU1 SoC module uses a 5 - 15 V DC power input for generating the on-board supply voltages
(0.72/0.85/0.9 V, 0.85/0.9 V, 0.9 V, 1.2 V, 1.8 V, 2.5 V, 3.3 V, and 5.0 V). Some of these voltages (1.8 V, 2.5 V, 3.3
V) are accessible on the module connector.
On revision 3 the Mercury+ XU1 SoC module suffered a major redesign around the power circuitry in order
to support all MPSoC device speedgrades, increase performance and support power converter synchro-
nization for noise-sensitive applications.
Table 14 describes the power supplies generated on the module.
D-0000-428-001 30 / 66 Version 13, 15.08.2019
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