BOOT BOOT PJTAG_EN# Mode Description Remarks
MODE1 MODE0 Straps [3:0]
0 0 1 0110 Boot from eMMC flash -
0 1 1 1110 Boot from SD card
(with an external SD 3.0
compliant level shifter;
only available when
VCC_CFG_MIO is 1.8 V)
Not supported (may be
supported in the future)
1 0 1 0010 Boot from QSPI flash -
1 1 1 0101 Boot from SD card (de-
fault mode)
-
1 1 0 1001 PJTAG boot mode
25
Not supported
in the standard
configuration
25
1 0 - 0000 JTAG boot mode Available only starting
with revision 4 mod-
ules in certain condi-
tions (refer to Section
3.6.4 for details).
Table 38: Boot Modes
3.6 JTAG
The Zynq Ultrascale+ devices include two separate JTAG controllers: the Zynq Ultrascale+ TAP and the ARM
DAP. The first one uses the PS dedicated JTAG pins and has access to both PS and PL and the second one
uses the PS PJTAG pins and is used for loading programs, system test, and PS debug.
Details on JTAG and on system test and debug are available in the Zynq UltraScale+ MPSoC Technical Ref-
erence Manual [19].
On modules equipped with ES1 (engineering samples 1) MPSoC devices, PJTAG boot mode is required in
order to program the FPGA and download a program to one of the ARM processors via JTAG.
Certain Xilinx tool versions support QSPI flash programming via JTAG only when JTAG boot mode is used
(unavailable in the standard configurations of the Mercury+ XU1 SoC module). Alternatively, the QSPI flash
can be programmed in u-boot or Linux by the SPI controller in the PS or from an SPI external master.
3.6.1 JTAG on Module Connector
The PL and the PS JTAG interfaces are connected into one single chain available on the module connector.
The PS_JTAG pins are used by the Zynq Ultrascale+ TAP controller - the controller has full functionality only
after the PS boot is complete. In order to enable the ARM DAP controller, special commands must be sent
to the Zynq Ultrascale+ TAP.
25
Starting with revision 3, PJTAG boot mode is not supported anymore on any configuration.
D-0000-428-001 52 / 66 Version 13, 15.08.2019
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