Figure 16: Pull-Up During Configuration (PUDC) and Power-on Reset Delay Override (PORSEL) Resistors - Assembly
Drawing Bottom View (lower right part) for Revision 4 Modules
For details on the PUDC signal please refer to the Zynq UltraScale+ MPSoC Technical Reference Manual
[19].
3.4 Power-on Reset Delay Override
The power-on reset delay override MPSoC signal (POR_OVERRIDE) is pulled to GND on the module, setting
the PL power-on delay time to the default standard time.
If the application requires faster PL power-on delay time, this can be achieved by removing R203 component
and by mounting R202.
Figure 15 illustrates the configuration of the POR_OVERRIDE signal. Figure 16 indicates the location of the
pull-up/pull-down resistors on the module PCB - lower right part on the bottom view drawing.
For details on the POR_OVERRIDE signal please refer to the Zynq UltraScale+ MPSoC Technical Reference
Manual [19].
3.5 Boot Mode
The boot mode can be selected via two signals available on the module connector and a signal available on
the debug connector.
Table 38 describes the available boot modes on the Mercury+ XU1 SoC module. PJTAG_EN# signal is only
available on the optional debug connector. It has a 10 kΩ pull-up resistor to VCC_CFG_MIO, therefore it may
be left unconnected.
Note that starting with revision 3, the debug connector is not offered as an optional feature anymore. The
related circuitry has been completely removed and the PJTAG boot mode is not supported any longer.
Starting with revision 4, JTAG boot mode has been introduced to increase the usability with Xilinx tools,
which may report issues when programming the on-board QSPI flash or when loading the FPGA bitstream
in a non-JTAG boot mode.
D-0000-428-001 51 / 66 Version 13, 15.08.2019
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