2 Module Description
2.1 Block Diagram
Figure 1: Hardware Block Diagram
The main component of the Mercury+ XU6 SoC module is the Xilinx Zynq Ultrascale+ MPSoC device. Most
of its I/O pins are connected to the Mercury+ module connector, making up to 254 regular user I/Os avail-
able to the user. Further, up to 8 MGT pairs are available on the module connector, making possible the
implementation of several high-speed protocols such as PCIe Gen3/Gen2 ×4 and USB 3.0 (simultaneous
usage of all the interfaces is limited to the available hardware resources i.e. number of transceivers and lane
mapping).
The MPSoC device can boot from the on-board QSPI flash, from the eMMC flash or from an external SD
card. For development purposes, a JTAG interface is connected to Mercury module connector.
The available standard configurations include a 16 GB eMMC flash, a 64 MB quad SPI flash, up to 8 GB DDR4
SDRAM with ECC connected to the Processing System (PS).
The module is equipped with a Gigabit Ethernet PHY and two USB 2.0 PHYs, making it ideal for communi-
cation applications.
A real-time clock is available on the Xilinx Zynq Ultrascale+ MPSoC device.
D-0000-464-001 11 / 58 Version 02, 21.07.2021
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