3.5.1 JTAG on Module Connector
The PL and the PS JTAG interfaces are connected into one single chain available on the module connector.
The PS_JTAG pins are used by the Zynq Ultrascale+ TAP controller - the controller has full functionality only
after the PS boot is complete. In order to enable the ARM DAP controller, special commands must be sent
to the Zynq Ultrascale+ TAP.
The MPSoC device and the flash devices can be configured via JTAG from Xilinx SDK or Xilinx Vivado Hard-
ware Manager - for this operation, the ARM DAP must be enabled.
Signal Name Module Connector Pin PS Dedicated Pin Resistor
JTAG_TCK A-123 PS_JTAG_TCK 4.7 kΩ pull-up to VCC_CFG_MIO
JTAG_TMS A-119 PS_JTAG_TMS 4.7 kΩ pull-up to VCC_CFG_MIO
JTAG_TDI A-117 PS_JTAG_TDI 4.7 kΩ pull-up to VCC_CFG_MIO
JTAG_TDO A-121 PS_JTAG_TDO 4.7 kΩ pull-up to VCC_CFG_MIO
Table 34: JTAG Interface - PL and PS Access and Debug
3.5.2 External Connectivity
JTAG signals can be connected directly on the base board to a JTAG connector. No pull-up/pull-down re-
sistors are necessary. The VREF pin of the programmer must be connected to VCC_CFG_MIO.
It is recommended to add 22 Ω series termination resistors between the module and the JTAG header, close
to the source. Please refer to the Enclustra Module Pin Connection Guidelines for details on JTAG interface.
3.5.3 JTAG Boot Mode
The following steps are required in order to boot the module in JTAG mode:
• Set the boot mode selection signals for QSPI boot
• Short-circuit R206 (see Figure 14) while powering-up the module (in order to sample the MPSoC boot
selection pins correctly for JTAG boot mode)
Figure 14: JTAG Boot Mode Resistor - Assembly Drawing Top View (lower center part)
D-0000-464-001 46 / 58 Version 02, 21.07.2021
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