2.19.6 RGMII Delays Configuration
The Ethernet PHY is connected directly to the hard MAC controller present in the MPSoC device. In order
to achieve the best sampling eye for the RX and TX data, it is recommended to adjust the pad skew delays
as specified in Table 29. These values have been successfully tested on Enclustra side.
The delays can be adjusted by programming the RGMII pad skew registers of the Ethernet PHY; please refer
to the PHY datasheet for details.
PHY Register Name Register Value [binary] Delay Value
RXD0-RXD3 0111 0 ps
RX_DV 0111 0 ps
RX_CLK 01111 0 ps
TXD0-TXD3 0111 0 ps
TX_EN 0111 0 ps
GTX_CLK 11110 900 ps
Table 29: Gigabit Ethernet PHY Configuration - RGMII Delays
2.20 USB 2.0
Two USB 2.0 PHYs are available on the Mercury+ XU6 SoC module, both connected to the PS to I/O bank
502. USB PHY 0 can be configured as host or device, while USB PHY 1 can be used only as host.
If USB on-the-go (OTG) functionality is required, an assembly option is available, where the module connec-
tor pins A-131 (VBUS_HPD) and A-133 (ID_HDM) are connected to the USB PHY 0 pins 22 (VBUS) and 23 (ID)
instead of being connected to the second USB PHY to pins DM and DP. Please contact Enclustra support if
USB OTG is required for your application.
2.20.1 USB PHY Type
Table 30 describes the equipped USB PHYs device type on the Mercury+ XU6 SoC module.
PHY Type Manufacturer Type
USB3320C Microchip USB 2.0 PHY
Table 30: USB 2.0 PHY Type
2.20.2 Signal Description
The ULPI interface for the PHY 0 is connected to MIO pins 52-63, while the interface for the PHY 1 is con-
nected to MIO pins 64-75, both connected for use with the integrated USB controller.
D-0000-464-001 40 / 58 Version 02, 21.07.2021
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