Signal Name Connector Pin Package Pin FPGA Pin Type Description
PS_POR# A-132 P16 PS_POR_B Power-on reset
PS_SRST# A-124 N19 PS_SRST_B System reset
Table 20: Reset Resources
Please note that PS_POR# is automatically asserted if PWR_GOOD is low.
2.14 LEDs
There are four active-low user LEDs on the Mercury+ XU6 SoC module - all of them are connected to both
PS and PL.
It is recommended to drive the PL pin to a high impedance state before driving the PS pin and vice versa.
PS Signal PS Signal PL Signal PL Signal Remarks
Name Location Name Location
LED0#_PS AB19 (MIO24) LED0#_PL E7 User function/active-low
LED1#_PS AB21 (MIO25) LED1#_PL H2 User function/active-low
LED2#_PS AH17 (MIO7) LED2#_PL P9 User function/active-low
LED3#_PS AF17 (MIO8) LED3#_PL K5 User function/active-low
Table 21: User LEDs
In addition to the user LEDs, two status LEDs are equipped on the module, offering details on the configu-
ration process for debugging purposes.
PS Signal Name PS Signal Location Remarks
PS_ERROR P17 (PS_ERROR_OUT) Refer to Zynq UltraScale+ MPSoC Technical Reference
Manual [18]
PS_STATUS M20 (PS_ERROR_STATUS) Refer to Zynq UltraScale+ MPSoC Technical Reference
Manual [18]
Table 22: Status LEDs
2.15 DDR4 SDRAM (PS)
There is a single DDR4 SDRAM channel on the Mercury+ XU6 SoC module attached directly to the PS side
and is available only as a shared resource to the PL side.
The DDR4 SDRAM is connected to PS I/O bank 504. The memory configuration on the Mercury+ XU6 SoC
module supports ECC error detection and correction; the correction code type used is single bit error cor-
rection and double bit error detection (SEC-DED).
D-0000-464-001 34 / 58 Version 02, 21.07.2021
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