Table 5 includes information related to the total number of I/Os available in each I/O bank and possible
limitations.
Signal Name Sign. Pairs Differential Single- I/O Bank
ended
IO_B64_<...> 52 24 In/Out In/Out 64 (HP)
2
4 signals are routed via level
shifters (Refer to Section 2.9.2 for
details)
IO_B65_<...> 48 24 In/Out In/Out 65 (HP)
3
IO_B66_<...> 48 24 In/Out In/Out 66 (HP)
3
IO_BE_<...> 24 12 In/Out (no LVDS/LVPECL outputs
supported; internal differential ter-
mination not supported)
In/Out 25 (HD)
3
for ZU2/ZU3
45 (HD)
3
for ZU4/ZU5
Refer to Section 2.9.3 for details.
IO_BF_<...> 20 10 In/Out (no LVDS/LVPECL outputs
supported; internal differential ter-
mination not supported)
In/Out 26 (HD)
3
for ZU2/ZU3
46 (HD)
3
for ZU4/ZU5
Refer to Section 2.9.3 for details.
IO_BN_<...> 24 12 In/Out (no LVDS/LVPECL outputs
supported; internal differential ter-
mination not supported)
In/Out 24 (HD)
3
for ZU2/ZU3
44 (HD)
3
for ZU4/ZU5
Refer to Section 2.9.3 for details.
IO_BO_<...> 24 12 In/Out (no LVDS/LVPECL outputs
supported; internal differential ter-
mination not supported)
In/Out 44 (HD)
3
for ZU2/ZU3
43 (HD)
3
for ZU4/ZU5
Refer to Section 2.9.3 for details.
Total 240 118 - - -
Table 5: User I/Os
The multi-gigabit transceiver (MGT) are described in section 2.10.
2.9.2 I/O Pin Exceptions
The I/O pin exceptions are pins with special functions or restrictions (for example, when used in combination
with certain Mercury boards they may have a specific role).
3
HD = high density pins, HP = high performance pins; Refer to the Zynq UltraScale+ MPSoC Overview [22] for details.
D-0000-464-001 20 / 58 Version 02, 21.07.2021
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