• ZU4CG/ZU4EV/ZU5EV devices: 4 GTH MGTs @ 12.5 Gbit/sec and 2 reference input clock differential
pairs
• ZU4CG/ZU4EV/ZU5EV devices: PCIe Gen3 ×4 (Xilinx built-in PCIe integrated block using GTH lines)
• 4 GTR MGTs @ 6 Gbit/sec and 2 reference input clock differential pairs
• PCIe Gen2 ×4 (Xilinx built-in PCIe hard block using GTR lines)
• Up to 8 GB DDR4 SDRAM with ECC on PS side
• 64 MB quad SPI flash
• 16 GB eMMC flash
• 1 × Gigabit Ethernet PHYs
• 2 × USB 2.0 PHYs (host and host/device) or 1 × USB 2.0 OTG PHY
• USB 3.0 (Xilinx built-in USB 3.0 hard block using GTR lines)
• Real-time clock
• CAN, UART, SPI, I2C, SDIO/MMC
• Small form factor (65 × 54 mm)
• 5 to 15 V supply voltage
1.3 Deliverables
• Mercury+ XU6 SoC module
• Mercury+ XU6 SoC module documentation, available via download:
• Mercury+ XU6 SoC Module User Manual (this document)
• Mercury+ XU6 SoC Module Reference Design [2]
• Mercury+ XU6 SoC Module IO Net Length Excel Sheet [3]
• Mercury+ XU6 SoC Module FPGA Pinout Excel Sheet [4]
• Mercury+ XU6 SoC Module User Schematics (PDF) [5]
• Mercury+ XU6 SoC Module Known Issues and Changes [6]
• Mercury+ XU6 SoC Module Footprint (Altium, Eagle, Orcad and PADS) [7]
• Mercury+ XU6 SoC Module 3D Model (PDF) [8]
• Mercury+ XU6 SoC Module STEP 3D Model [9]
• Mercury Mars Module Pin Connection Guidelines [10]
• Mercury Master Pinout [11]
• Mercury Heatsink Application Note [17]
• Enclustra Build Environment [14] (Linux build environment; refer to Section 1.4.2 for details)
• Enclustra Build Environment How-To Guide [15]
1.4 Accessories
1.4.1 Reference Design
The Mercury+ XU6 SoC module reference design features an example configuration for the Zynq Ultra-
scale+ MPSoC device, together with an example top level HDL file for the user logic.
A number of software applications are available for the reference design, that show how to initialize the
peripheral controllers and how to access the external devices. Pre-compiled binaries are included in the
archive, so that the user can easily check that the hardware is functional.
The reference design can be downloaded from Github: https://github.com/enclustra.
1.4.2 Enclustra Build Environment
The Enclustra Build Environment (EBE) [14] enables the user to quickly set up and run Linux on any Enclustra
SoC module or system board. It allows the user to choose the desired target, and download all the required
binaries, such as bitstream and FSBL. It downloads and compiles all required software, such as U-Boot, Linux,
and BusyBox based root file system.
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