PHY Type Manufacturer Type
KSZ9031RNXIA Microchip (Micrel) 10/100/1000 Mbit
Table 27: Gigabit Ethernet PHY (PS) Type
2.19.2 Signal Description
Ethernet PHY is connected to ETH 0 controller from the PS I/O bank 501. One of the Ethernet TX data signals
is shared with the PCIe reset signal (PERST#); if the application requires a hard PCIe block, the ETH interface
is not available. Refer to Section 2.9.2 for details on the PERST# connection.
Warning!
Gigabit Ethernet interface is not available when the PCIe endpoint in the PS is used (because of the
PERST# connection).
The interrupt output of the Ethernet PHY is connected to the I2C interrupt line, available on MIO12 pin.
2.19.3 External Connectivity
The Ethernet signal lines can be connected directly to the magnetics. Please refer to the Enclustra Module
Pin Connection Guidelines [10] for details regarding the connection of Ethernet signals.
2.19.4 MDIO Address
The MDIO address assigned to the ETH PHY is 3, and the PHY can be configured via MIO pins 76-77.
2.19.5 PHY Configuration
The configuration of the Ethernet PHY is bootstrapped when the PHYs are released from reset. Make sure all
I/Os on the RGMII interface are initialized and all pull-up or pull-down resistors are disabled at that moment.
The bootstrap options of the Ethernet PHYs are set as indicated in Table 28.
Pin Signal Value Description
MODE[3-0] 1110 RGMII mode: advertise all capabilities (10/100/1000, half/full duplex) ex-
cept 1000Base-T half duplex.
PHYAD[2-0] 011 MDIO address 3
Clk125_EN 0 125 MHz clock output disabled
LED_MODE 1 Single LED mode
LED1/LED2 1 Active-low LEDs
Table 28: Gigabit Ethernet PHY Configuration - Bootstraps
For the Ethernet PHY configuration via the MDIO interface, the MDC clock frequency must not exceed 2
MHz.
D-0000-464-001 39 / 58 Version 02, 21.07.2021
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