The GTH MGTs on the MPSoC device support data rates of 12.5 Gbit/sec.
The MPSoC devices equipped on the Mercury+ XU6 SoC module variants 4EV/5EV can support up to two
integrated PCIe Gen3 interfaces on the PL side, implemented using GTH transceivers. Simultaneous usage
of these interfaces is limited to the available hardware resources (number of transceivers and lane mapping).
Warning!
It is recommended to use redrivers on the base board for PCIe Gen3 or other high-speed interfaces
implementations, and to perform channel simulation.
GTR Transceivers
There are four GTR MGT pairs and two reference input clock differential pairs on the Mercury+ XU6 SoC
module connected to I/O bank 505; these are routed by default to module connector B - refer to Section
2.9.2 for details on the assembly variants and MGT connectivity.
The naming convention for the GTR MGT I/Os is:
MGTPS_<FUNCTION>_<P
ACKAGE_PIN>_<POLARITY>.
For example, MGTPS_RX2_B28_N is located on pin B28 of PS GTR bank (bank 505), it is a receive pin and it
has negative polarity.
All Mercury+ XU6 SoC module variants support the implementation of a PCIe Gen2 ×4 interface.
Please note that when the PCIe hard block is used, it is not possible to use the Ethernet interface. The
Ethernet PHY is connected to ETH 0 controller from the PS I/O bank 501; one of the Ethernet TX data signals
is shared with the PCIe reset signal (PERST#). Refer to Sections 2.9.2 and 2.9.7 for details on the PERST#
connection.
The GTR pairs support data rates of 6 Gbit/sec and can be used for the implementation of several interfaces
such as PCIe Gen2 ×4, USB 3.0, DisplayPort, SATA, or Ethernet SGMII. Please refer to the Zynq UltraScale+
MPSoC Technical Reference Manual [18] and to the Zynq UltraScale+ MPSoC Overview [22] for details.
A 100 MHz LVDS oscillator and a 27 MHz CMOS oscillator provide reference clock inputs to the PS GTR bank
505. Please refer to Section 2.12 for details.
Warning!
The maximum data rate on the MGT lines on the Mercury+ XU6 SoC module depends on the routing
path for these signals. Adequate signal integrity over the full signal path must be ensured when using
MGTs at high performance rates.
Warning!
No AC coupling capacitors are placed on the Mercury+ XU6 SoC module on the MGT lines - make sure
capacitors are mounted, if required, on the base board (close to the module pins), to prevent MGT lines
from being damaged.
D-0000-464-001 28 / 58 Version 02, 21.07.2021
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