Fuji Electric SPH Series - Page 33

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Section 1 Specications
2) External interrupt factor occurrence %MW1.61492 to %MW1.61497
3) Interrupt mask status ag %MW1.61498
Address Name Description Attribute
%MX1.61492.0
External interrupt factor
occurrence for rising edge 0
ON when an interrupt factor occurs due to detection of a rising
edge of the signal of the input terminals X0 to X15 in the main
unit. This memory can be read and reset (written) from an
application.
R/W
| |
%MX1.61492.15
External interrupt factor
occurrence for rising edge 15
%MX1.61493.0
|
%MX1.61494.15
Not used
%MX1.61495.0
External interrupt factor
occurrence for falling edge 0
ON when an interrupt factor occurs due to detection of a falling
edge of the signal of the input terminals X0 to X15 in the main
unit. This memory can be read and reset (written) from an
application.
R/W
| |
%MX1.61495.15
External interrupt factor
occurrence for falling edge 15
%MX1.61496.0
|
%MX1.61497.15
Not used
Address Name Description Attribute
%MX1.61498.0
Interrupt mask status ag for
level 0 task
ON when interrupt is disabled in the level 0 task.
R
%MX1.61498.1
Interrupt mask status ag for
level 1 task
ON when interrupt is disabled in the level 1 task.
%MX1.61498.2
Interrupt mask status ag for
level 2 task
ON when interrupt is disabled in the level 2 task.
%MX1.61498.3
Interrupt mask status ag for
level 3 task
ON when interrupt is disabled in the level 3 task.
%MX1.61498.4
Interrupt mask status ag for
level 4 task
ON when interrupt is disabled in the level 4 task.
%MX1.61498.5
|
%MX1.61498.9
Not used
%MX1.61498.10
Interrupt mask status ag for
level 10 to 19 tasks
ON when interrupt is disabled in the level 10 to 19 tasks.
R
%MX1.61498.11
|
%MX1.61498.15
Not used