GW Instek APS-1102A - Figure 6-5. Standard Event Status Register; Standard Event Status

APS-1102A User Manual
APS-1102A
6-52
6.5.2 Standard event status
The structure of the standard event status register is shown in Figure 6-5 below.
Power on (PON)
User request (URQ)
Command error (CME)
Execution error (EXE)
Device specific error (DDE)
Query error (QYE)
Request control (RQC)
Operation complete (OPC)
7
6
5
4
3
2
1
0
ESR (standard event register)
7
6
5
4
3
2
1
0
Logical OR
ESE (standard event enable register)
Standard event status summary
Status byte (bit 5)
Figure 6-5. Standard Event Status Register
The definition of the standard event status register is listed in Table6-15. Bits in the standard event status
register become valid when 1 is set to the standard event status enable register, and the ORed result of the
valid bits is reflected in the ESB bit of the status bit register.
The standard event status register can be read by an ESR? query.
All of the bits are cleared when they are read by an *ESR? query, when a *CLS command is executed, or
when the power is turned on again (except that the PON bit is set to 1 when the power is turned on again).